Increased demand for computer memory has driven the memory industry to introduce various configurations and designs of transistors to fit more memory into a given area and, therefore, to create memory devices with increased memory density. One such memory device with the potential for increased memory density is the so-called “vertical memory” device. A vertical memory device includes an array of transistors with each transistor extending generally perpendicular to a substrate, such as a silicon substrate. Each transistor of the vertical memory device can include silicon and may have several doped regions. For example, a bottom region may be n-doped, a middle region may be p-doped, and a top region may be n-doped. The bottom, n-doped region may be a source region and the top, n-doped region may be a drain region. A gate material, such as a gate oxide, may be formed along a vertical sidewall of the transistor to cover the middle, p-doped region and to contact a portion of the top and bottom n-doped regions, respectively. A buried metal data/sense line (e.g., a digit or bit line) for reading and writing data to the transistors may contact multiple source regions and may extend across multiple transistors in a first direction. An access line (e.g., a word line) for reading and writing data to the transistors may be formed over the gate material along the vertical sidewall of the transistor and may extend across multiple transistors in a second direction that is generally perpendicular to the first direction.
Buried digit lines contacting adjacent source regions may be separated by a trench extending in the first direction. Access lines contacting transistors adjacent to each other in the first direction may be separated by another trench that extends in the second direction. Such trenches may generally be filled with one or more dielectric (i.e., non-conductive) material, such as silicon oxide, silicon nitride, air, etc., for providing electrical isolation between adjacent bit lines and access lines, respectively.
A digit line end region may be located proximate an edge of the array. Conventionally, the digit line end region includes a silicon pillar extending vertically between each buried digit line and a digit line contact. In addition to forming the substrate with the doped source and drain regions in the array region described above, the silicon pillar in the buried digit line end region is heavily doped so as to be conductive for electrically connecting each buried digit line to each digit line contact. Such a doped silicon pillar may present several problems in manufacturing a vertical memory device and possibly in the device performance. For example, the doped silicon may add to electrical resistance between the digit line contact and the buried digit line due to metal-to-silicon contacts. If the silicon pillar is doped too heavily, then the dopant may extend into the substrate and electrical separation between adjacent digit lines may be lost. Furthermore, the doping may cause crystal damage in the silicon pillar. Crystal damage may further increase resistance across the doped region such as by increased oxygen absorption during subsequent processing. In addition, device performance is negatively affected by non-uniform doping through the depth of the silicon pillar. However, uniform doping of the silicon pillar may be difficult and expensive to achieve. Furthermore, there may be some variation in the depth of the buried digit lines across vertical memory devices, which adds to the difficulties of doping each silicon pillar to the appropriate depth to form an electrical connection. Furthermore, the dopants implanted in the silicon pillar may require activation through additional processing (e.g., curing, annealing, etc.), which adds to the manufacturing difficulty and cost.